MC14049BDG Просмотр технического описания (PDF) - ON Semiconductor
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MC14049BDG Datasheet PDF : 8 Pages
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MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P−Channel and N−Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, VDD.
The input−signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS−to−TTL/DTL converter
(VDD = 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
Features
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• VIN can exceed VDD
• Meets JEDEC B Specifications
• Improved ESD Protection On All Inputs
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage Range
−0.5 to +18.0 V
Vin Input Voltage Range (DC or Transient) −0.5 to +18.0 V
Vout Output Voltage Range (DC or Transient) −0.5 to VDD + V
0.5
Iin
Input Current (DC or Transient) per Pin
± 10
mA
Iout Output Current (DC or Transient) per Pin
± 45
mA
PD Power Dissipation, per Package (Note 1)
mW
(Plastic)
825
(SOIC)
740
TA
Ambient Temperature Range
−55 to +125 °C
Tstg Storage Temperature Range
−65 to +150 °C
TL
Lead Temperature (8−Second Soldering)
260
°C
1. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high−impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 16
P SUFFIX
CASE 648
1
MC140xxBCP
AWLYYWW
SOIC−16
D SUFFIX
CASE 751B
16
140xxB
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
14
0xxB
ALYW
1
SOEIAJ−16
F SUFFIX
CASE 966
16
MC140xxB
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
February, 2005 − Rev. 5
Publication Order Number:
MC14049B/D
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