JTS8388B-1V1B Просмотр технического описания (PDF) - Unspecified
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JTS8388B-1V1B Datasheet PDF : 62 Pages
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TS8388B
5.4 Timing Diagrams
Figure 5-1. TS8388B Timing Diagram (1 Gsps Clock Rate), Data Ready Reset, Clock Held at Low Level
(VIN, VINB)
X
N-1
TA = 250 ps TBC
XN
X
X
N+1
N+2
TC = 1000 ps
X
N+3
X
N+4
X
N+5
TC1 TC2
(CLK, CLKB)
DIGITAL
OUTPUTS
1360 ps
1000 ps
DATA
N-5
TPD: 4.0 Clock periods
DATA
N-4
DATA
N-3
TOD = 1360 ps
DATA
N-2
DATA
N-1
DATA
N
N+1
Data Ready
(DR, DRB)
TDR = 1320 ps
TDR = 1320 ps
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
DRRB
TRDR = 720 ps
1 ns (min)
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
Figure 5-2. TS8388B Timing Diagram (1 Gsps Clock Rate), Data Ready Reset, Clock Held at High Level
(VIN, VINB)
XN-1
TA = 250 ps TBC
XN
X
N+1
X
N+2
X
TC = 1000 ps
TC1 TC2
X
N+4
X
N+5
(CLK, CLKB)
DIGITAL
OUTPUTS
1360 ps
1000 ps
TDR = 1320 ps
Data Ready
(DR, DRB)
DATA
N-5
TPD: 4.0 Clock periods
DATA
N-4
DATA
N-3
TDR = 1320 ps
TOD = 1360 ps
DATA
N-2
DATA
N-1
DATA
N
DATA
N+1
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
DRRB
TRDR = 720 ps
1 ns (min)
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
10
0860F–BDC–12/09
e2v semiconductors SAS 2009
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