ESDALC6V1W5(2002) Просмотр технического описания (PDF) - STMicroelectronics
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ESDALC6V1W5 Datasheet PDF : 9 Pages
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ESDALC6V1W5
TECHNICAL INFORMATION
1. ESD protection by ESDALC6V1W5
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
As a transient voltage suppressor, ESDALC6V1W5 is an ideal choice for ESD protection by suppressing
ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is
prevented on the device protected by ESDALC6V1W5.
ESDALC6V1W5 serves as a parallel protection elements, connected between the signal line and ground.
As the transient rises above the operating voltage of the device, the ESDALC6V1W5 becomes a low
impedance path diverting the transient current to ground.
The clamping voltage is given by the following formula:
VCL = VBR + Rd.IPP
As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A1: ESD clamping behavior
RG IPP
Rd
VG
VBR
ESD surge
ESDALC6V1W5
V(i/o)
RL OAD
Device
to be
protected
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical
resistance value Rd. By taking into account the following hypothesis:
Rg > Rd and Rload > Rd
we have:
( ) V i / o
= VBR
+
Rd
× Vg
Rg
The results of the calculation done Vg = 8kV, Rg = 330Ω (IEC61000-4-2 standard), VBR = 6.1V (min) and
Rd = 1.1Ω (typ.) give:
V (i / o ) = 32,8Volts
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.
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