ADMC201AP Просмотр технического описания (PDF) - Analog Devices
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ADMC201AP Datasheet PDF : 15 Pages
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ADMC201
Table I. Timing Specifications (VDD = 5 V, ؎ 5%; TA = –40؇C to +85؇C)
Number Symbol
Timing Requirements
Min
Max
1
tperclk
2
tpwhclk
3
tpwlclk
4
tsucsb_wrb
5
tsuaddr_wrb
6
tsudata_wrb
7
thdwrb_data
8
thdwrb_addr
9
thdwrb_csb
10
tpwlwrb1
11
tpwhwrb1
12
thdwrb_clk_h1
13
tsuwrb_clk_h1
14
tsuwrb_clk_l1
15
thdclk_wrb_l1
16
tsucsb_rdb
17
tsuaddr_rdb
18
9 thdrdb_addr
19
thdrdb_csb
20
tpwlrdb
21
tpwhrdb
22
tsurdb_clk_h
23
thdrdb_clk_h
24
tpwlresetb
CLK Period
CLK Pulsewidth, High
CLK Pulsewidth, Low
CS Low before Falling Edge of WR
ADDR Valid before Falling Edge of WR
DATA Valid before Rising Edge of WR
DATA Hold after Rising Edge of WR
ADDR Hold after Rising Edge of WR
CS Hold after Rising Edge of WR
WR Pulsewidth, Low
WR Pulsewidth, High
WR Low after Rising Edge of CLK
WR High before Rising Edge of CLK
WR High before Falling Edge of CLK
WR High after Falling Edge of CLK
CS Low before Falling Edge of RD
ADDR Valid before Falling Edge of RD
ADDR Hold after Rising Edge of RD
CS Hold after Rising Edge of RD
RD Pulsewidth, Low
RD Pulsewidth, High
RD Low before Rising Edge of CLK
RD Low after Rising Edge of CLK
RESET Pulsewidth, Low
NOTE
1All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).
40
160
20
20
0
0
13
4.5
4.5
4.5
20
20
7
7
10
10
0
0
0
0
20
20
7.5
7.5
2 × tperclk
Number
25
26
27
28
Symbol
tdlyrdb_data
thdrdb_data
tpwh_pio
tpwl_pio
Switching Characteristics
DATA Valid after Falling Edge of RD
DATA Hold after Rising Edge of RD
Digital I/O Pulsewidth, High
Digital I/O Pulsewidth, Low
Min
0
2 × tperclk
2 × tperclk
Max
23
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
CLK
1
2
3
Figure 1. Clock Input Timing
CLK
RESET
24
Figure 2. Reset Input Timing
CLK
CS
12
15 13
9
8
A0–A3
WR
11
14
10
DATA
4
6
5
7
NOTE:
ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN
ONE SYSTEM CLOCK CYCLE (i.e., 0 WAIT STATES)
Figure 3. Write Cycle Timing Diagram
REV. B
–3–
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