CXL1517M/1518M
Pin Description
Pin No. Symbol
1
VSS
2
IN-B
3
ABBL
4
VDD
5
IN-C
6
CLP
7
VDD
8
OUT-C
9
VGG
10 OUT-B
11 OUT-A
12 CDS
13
VSS
14
VSS
15 XDL2
16 XDL1
17
VDD
18 ABCN
19 ABOVF
20 IN-A
I/O
Description
Comment
— GND
Analog
I Signal input B channel (Y)
O Autobias DC output for Y signal
Black level bias
— Power supply
Analog
I Signal input C channel (Y)
Black level bias
at no clamp > 100k
I Clamp pulse input
> 100k
— Power supply
Output circuit
O Signal output C channel
O Output circuit bias DC output
O Signal output B channel
O Signal output A channel
O DC output for CDS
— GND
Output circuit
— GND
Timing
I Clock pulse input 2
> 100k
I Clock pulse input 1
> 100k
— Power supply
Timing
O Autobias DC output for C signal
Center level bias
O Autobias DC output for overflow prevention circuit
I Signal input A channel (C)
Center level bias
at no clamp > 100k
–3–