AD676JDZ Просмотр технического описания (PDF) - Analog Devices
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AD676JDZ Datasheet PDF : 17 Pages
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AD676
Pin Name
Type
1–6 BIT 11-BIT 16 DO
7
BUSY
DO
8
CAL
DI
9
SAMPLE
DI
10
CLK
DI
11
DGND
P
12
VCC
P
13
AGND
P/AI
14
AGND SENSE AI
15
VIN
AI
16
VREF
AI
17
VEE
P
18
VDD
P
19–28 BIT 1–BIT 10 DO
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
PIN DESCRIPTION
Description
BIT 11–BIT 16 represent the six LSBs of data.
Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.
BUSY should be buffered when capacitively loaded.
Calibration Control Pin (Asynchronous).
VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE controls the state
of the internal sample-hold amplifier and the falling edge initiates conversion (see “Conver-
sion Control” paragraph). During calibration, SAMPLE should be held LOW. If HIGH dur-
ing calibration, diagnostic information will appear on the two LSBs (Pins 5 and 6).
Master Clock Input. The AD676 requires 17 clock cycles to execute a conversion.
Digital Ground.
+12 V Analog Supply Voltage.
Analog Ground.
Analog Ground Sense.
Analog Input Voltage.
External Voltage Reference Input.
–12 V Analog Supply Voltage. Note: the lid of the ceramic package is internally connected to
VEE.
+5 V Logic Supply Voltage.
BIT 1–BIT 10 represent the ten MSB of data.
BIT 11 1
BIT 12 2
BIT 13 3
BIT 14 4
BIT 15 5
BIT 16 (LSB) 6
BUSY 7
CAL 8
SAMPLE 9
CLK 10
DGND 11
VCC 12
AGND 13
AGND SENSE 14
AD676
TOP VIEW
(Not to Scale)
28 BIT 10
27 BIT 9
26 BIT 8
25 BIT 7
24 BIT 6
23 BIT 5
22 BIT 4
21 BIT 3
20 BIT 2
19 BIT 1 (MSB)
18 VDD
17 VEE
16 VREF
15 VIN
Package Pinout
VIN 15
AGND SENSE 14
VREF 16
AGND 13
INPUT
BUFFERS
16-BIT
DAC
CAL
DAC
ANALOG
CHIP
COMP
LOGIC & TIMING
LEVEL TRANSLATORS
DIGITAL
CHIP
CAL 8
SAMPLE 9
CLK 10
MICRO-CODED
CONTROLLER
SAR
PAT
GEN
ALU
RAM
7 BUSY
1
L
A
6
T
BIT 1 – BIT 16
C
19
H
28
AD676
Functional Block Diagram
–6–
REV. A
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