AD676JDZ Просмотр технического описания (PDF) - Analog Devices
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AD676JDZ Datasheet PDF : 17 Pages
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AD676
TIMING SPECIFICATIONS(TMIN to TMAX VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10%, VREF = 10.0 V)1
Parameter
Symbol
Min
Typ
Max
Units
Conversion Time2
CLK Period3
Calibration Time
Sampling Time (Included in tC)
CAL to BUSY Delay
BUSY to SAMPLE Delay
SAMPLE to BUSY Delay
CLK HIGH4
CLK LOW4
SAMPLE LOW to 1st CLK Delay
SAMPLE LOW
Output Delay
Status Delay
CAL HIGH Time
tC
tCLK
tCT
tS
tCALB
tBS
tSB
tCH
tCL
tSC
tSL
tOD
tSD
tCALH
10
1000
µs
480
ns
85,530
tCLK
2
µs
75
150
ns
2
µs
15
100
ns
50
ns
50
ns
50
ns
100
ns
125
200
ns
50
ns
50
ns
NOTES
1See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion time is specified to account for the droop of the
internal sample/hold function. Longer conversion times may degrade performance. See “General Conversion Guidelines” for additional explanation of maximum con-
version time.
3580 ns is recommended for optimal accuracy over temperature.
4tCH + tCL = tCLK and must be greater than 480 ns.
tCALH
CAL
tCALB
t CT
BUSY
t CLK
t CH
t OD
CLK
tCL
Figure 1. Calibration Timing
tS
SAMPLE
(INPUT) tSC
CLK
(INPUT)
BIT 1 – BIT 16
(OUTPUTS)
tC
tSL
tCL
1
2
3
4
5
t CLK
(PREVIOUS CONVERSION)
BUSY
(OUTPUT)
tBS
tSB
13 14 15 16
t CH
t OD
17
(NEW DATA)
tSD
Figure 2a. General Conversion Timing
tS
SAMPLE
(INPUT) tSC
CLK
(INPUT)
BIT 1 – BIT 16
(OUTPUTS)
tC
tSL
t CL
1
2
3
4
5
t CLK
(PREVIOUS CONVERSION)
BUSY
(OUTPUT)
tBS
tSB
tS
13 14 15 16
t CH
t OD
17
(NEW DATA)
tSD
Figure 2b. Continuous Conversion Timing
–4–
REV. A
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