ADM1023
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted. (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SMBus Interface (See Figure 2)
Logic Input High Voltage, VIH
STBY, SCLK, SDATA
VDD = 3.0 V to 5.5 V
2.2
−
−
V
Logic Input Low Voltage, VIL
STBY, SCLK, SDATA
VDD = 3.0 V to 5.5 V
−
−
0.8
V
SMBus Output Low Sink Current
SDATA Forced to 0.6 V
6.0
−
−
mA
ALERT Output Low Sink Current
ALERT Forced to 0.4 V
1.0
−
−
mA
Logic Input Current, IIH, IIL
SMBus Input Capacitance, SCLK, SDATA
−1.0
−
+1.0
mA
−
5.0
−
pF
SMBus Clock Frequency
−
−
400
kHz
SMBus Clock Low Time, tLOW
tLOW between 10% Points
1.3
−
−
ms
SMBus Clock High Time, tHIGH
tHIGH between 90% Points
0.6
−
−
ms
SMBus Start Condition Setup Time,
tSU:STA
0.6
−
−
ms
SMBus Start Condition Hold Time, tHD:STA Time from 10% of SDATA to 90% of SCLK
0.6
−
−
ms
SMBus Stop Condition Setup Time, tSU:STO
Time from 90% of SCLK to 10% of SDATA
0.6
−
−
ms
SMBus Data Valid to SCLK Rising Edge
Time, tSU:DAT
Time for 10% or 90% of SDATA to 10% of SCLK
100
−
−
ns
SMBus Bus Free Time, tBUF
Between Start/Stop Condition
1.3
−
−
ms
SCLK SDATA Rise Time, tR MAX
Master Clocking in Data
−
−
300
ns
SCLK SDATA Fall Time, tF MAX
VDD = 0 V
1. TMAX = 120C, TMIN = 0C
2. TD is the temperature of the remote thermal diode; TA, TD = 60C to 100C
3. Operation at VDD = 5.0 V guaranteed by design; not production tested
4. Guranteed by design; not production tested
−
−
300
ns
tLOW
tR
SCL
tHD;STA
tHD;DAT
SDA
tBUF
P
S
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 2. Diagram for Serial Bus Timing
tSU;STO
P
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