M48T59-70MH1(2008) Просмотр технического описания (PDF) - STMicroelectronics
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M48T59-70MH1 Datasheet PDF : 32 Pages
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Operation modes
M48T59, M48T59Y, M48T59V
2.2
Write mode
The M48T59/Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; however, if the output bus has been activated by a
low on E and G a low on W will disable the outputs tWLQZ after W falls.
Figure 6. Write enable controlled, write mode AC waveforms
tAVAV
A0-A12
VALID
tAVWH
) E
roduct(s W
bsolete P DQ0-DQ7
tAVEL
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI01386
) - O Figure 7. Chip enable controlled, write mode AC waveforms
roduct(s A0-A12
Obsolete P E
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
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