AD5304ACPZ-REEL7 Просмотр технического описания (PDF) - Analog Devices
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AD5304ACPZ-REEL7
Analog Devices
AD5304ACPZ-REEL7 Datasheet PDF : 24 Pages
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Data Sheet
AD5304/AD5314/AD5324
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
Limit at TMIN, TMAX
VDD = 2.5 V to 3.6 V
VDD = 3.6 V to 5.5 V
40
33
16
13
16
13
16
13
5
5
4.5
4.5
0
0
80
33
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
t1
SCLK
SYNC
DIN
t8
t4
t3
t2
t7
t6
t5
DB15
DB0
Figure 2. Serial Interface Timing Diagram
Rev. H | Page 5 of 24
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