74HC107 Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC107 Datasheet PDF : 18 Pages
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Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
6. Functional description
Table 3. Function table[1]
Input
Output
R
CP
J
K
Q
Q
L
X
X
X
L
H
H
h
h
q
q
H
l
h
L
H
H
h
l
H
L
H
l
l
q
q
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
7. Limiting values
Operating mode
asynchronous reset
toggle
load 0 (reset)
load 1 (set)
hold (no change)
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to VCC + 0.5 V
Tamb = 40 C to +125 C
SO14 package
0.5
[1]
-
[1]
-
-
-
50
65
+7.0 V
20 mA
20 mA
25 mA
50 mA
- mA
+150 C
[2]
-
500 mW
(T)SSOP14 package
[3]
-
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© Nexperia B.V. 2017. All rights reserved
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