74HC107 Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC107 Datasheet PDF : 18 Pages
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Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
5. Pinning information
5.1 Pinning
+&
+&7
-
4
4
.
4
4
*1'
9&&
5
&3
.
5
&3
-
DDD
Fig 4. Pin configuration SO14 and (T)SSOP14
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1J, 2J
1, 8
1Q, 2Q
2, 6
1Q, 2Q
3, 5
1K, 2K
4, 11
1CP, 2CP
12, 9
1R, 2R
13, 10
GND
7
VCC
14
Description
synchronous J input
complement output
true output
synchronous K input
clock input (HIGH-to-LOW edge-triggered)
asynchronous reset input (active LOW)
ground (0 V)
supply voltage
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© Nexperia B.V. 2017. All rights reserved
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