SI5332A-C-GM2R Просмотр технического описания (PDF) - Silicon Laboratories

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SI5332A-C-GM2R

6/8/12-Output Any-Frequency Clock Generator

Silicon Laboratories 

Si5332 Data Sheet

Functional Description

3. Functional Description

The Si5332 is a high-performance, low-jitter clock generator capable of synthesizing up to twelve user-programmable clock frequencies

up to 312.5 MHz. The device supports free run operation using an external or embedded crystal, or it can lock to an external clock

signal. The output drivers support up to twelve differential clocks or twenty four LVCMOS clocks, or a combination of both. The output

drivers are configurable to support common signal formats, such as LVPECL, LVDS, HCSL, and LVCMOS. VDDO pins are provided for

versatility, which can be set to 3.3 V, 2.5 V, 1.8 V or 1.5 V (CMOS only) to power the multi-format output drivers. The core voltage

supply (VDD) accepts 3.3 V, 2.5 V, or 1.8 V and is independent from the output supplies (VDDOxs). Using its two-stage synthesis archi-

tecture and patented high-resolution low-jitter MultiSynth technology, the Si5332 can generate an entire clock tree from a single device.

The Si5332 combines a wideband PLL with next generation MultiSynth technology to offer the industry’s highest output count high per-

formance programmable clock generator, while maintaining a jitter performance of 230 fs RMS. The PLL locks to either an external

16-50 MHz crystal or an embedded 50 MHz crystal for generating for generating free-running clocks or to an external clock (CLKIN_2/

CLKIN_2# or CLKIN_3/CLKIN_3#) for generating synchronous clocks. In free-run mode, the oscillator frequency is multiplied by the

PLL and then divided down either by an integer divider or MultiSynth for fractional synthesis.

The Si5332 features user-defined universal hardware input pins which can be configured in the ClockBuilder Pro software utility. Uni-

versal hardware pins can be used for OE, spread spectrum enable, input clock selection, output frequency selection, or I2C address

select. If additional hardware input pins are needed, a user can define a different clock output as universal hardware input pins instead

using ClockBuilder Pro.

The device provides the option of storing a user-defined clock configuration in its non-volatile memory (NVM), which becomes the de-

fault clock configuration at power-up. To enable in-system programming, a power up mode is available through OTP which powers up

the chip in an OTP defined default mode but with no outputs enabled. This allows a host processor to first write a user defined subset of

the registers and then restart the power-up sequence to activate the newly programmed configuration without re-downloading the OTP.

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