650R-14 Просмотр технического описания (PDF) - Integrated Device Technology
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650R-14 Datasheet PDF : 7 Pages
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ICS650-14
NETWORKING SYSTEM CLOCK
CLOCK SYNTHESIZER
Pin Assignment
Table 2
SELB0
1
X2
2
X1/ICLK
3
VDD
4
SELB1
5
GND
6
CLKB
7
CLKC
8
CLKA5
9
25M
10
20
SELC
19
SELA0
18
CLKA2
17
CLKA3
16
VDD
15
SELA1
14
GND
13
CLKA4
12
CLKA1
11
OE
20-pin (150 mil) SSOP
SELB1
0
0
0
1
1
1
SELB0
0
M
1
0
M
1
CLKB
30
27
48
83.33
19.44
80
Pin Descriptions
Table 1
SELA1
0
0
0
M
M
M
1
1
1
SELA0
0
M
1
0
M
1
0
M
1
CLKA1:4
33.33
50
66.67
100
33.33
50
33.33
25
66.67
CLKA5
66.66
75
133.33
33.33
83.33
125
100
75
100
Table 3
SELC
0
M
1
CLKC
CLKB/4
62.5
125
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Pin
Number
1
2
Pin
Name
SELB0
X2
3
X1/ICLK
4
VDD
5
SELB1
6
GND
7
CLKB
8
CLKC
9
CLKA5
10
25M
11
OE
12
CLKA1
Pin
Type
TI
XO
XI
P
I(Pu)
P
O
O
O
Ou
I(Pu)
O
Pin Description
Select pin for CLKB. See table 2.
Crystal connection. Connect to a 25 MHz crystal or leave unconnected for clock
input.
Crystal connection. Connect to a 25 MHz fundamental crystal or clock input.
Connect to 3.3 V or 5 V. Must be same as other VDDs.
Select pin for CLK B. See table 2.
Connect to ground.
Selectable clock output. See table 2.
Selectable clock output. See table 3.
Selectable clock output. See table 1.
25 MHz clock output.
Output enable. Tri-states all outputs when low. Internal pull-up.
Selectable clock output. See table 1.
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
2
ICS650-14 REV G 110409
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