NETWORKING SYSTEM CLOCK
DATASHEET
ICS650-14
Description
The ICS650-14 is a low-cost, low-jitter, high-performance
clock synthesizer customized for networking systems
applications. Using analog/digital Phase-Locked Loop (PLL)
techniques, the device accepts a 25 MHz clock or
fundamental mode crystal input to produce multiple output
clocks of one fixed 25 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable clocks. All
output clocks are frequency locked together. All of the
ICS650-14 outputs have zero ppm synthesis error.
Block Diagram
Features
• Packaged in 20-pin (150 mil) SSOP (QSOP)
• 25 MHz fundamental crystal clock or clock input
• One fixed output clock of 25 MHz
• One bank of four frequency selectable output clocks
• Three frequency selectable clocks outputs
• Zero ppm synthesis error in all clocks
• Ideal for networking systems
• Full CMOS output swing
• Advanced, low-power sub-micron CMOS process
• Operating voltage of 3.3 V or 5 V
• Industrial temperature range available
• Pb-free, RoHS compliant package
VDD
2
2
SELA 0:1
2
SELB 0:1
SELC
C lock
Synthesis and
C o n tro l
C irc u itry
X 1 /IC L K
25 MHz
Crystal or C lock
X2
Crystal
B u ffe r/
Crystal
O scillator
O ptional crystal capacitors are show n and m ay be
required for tuning of initial accuracy (determ ined
once per board)
2
GND
4
CLKA 1:4
CLKA5
CLKB
CLKC
25 MHz
O E (all outputs)
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
1
ICS650-14 REV H 051310