85304-01 Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
производитель
85304-01 Datasheet PDF : 15 Pages
| |||
Low Skew, 1-to-5, Differential-to-3.3V
LVPECL Fanout Buffer
85304-01
Data Sheet
General Description
The 85304-01 is a low skew, high performance 1-to-5
Differential-to-3.3V LVPECL fanout buffer. The 85304-01 has two
selectable clock inputs. The CLKx, nCLKx pairs can accept most
standard differential input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs during
asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
85304-01 ideal for those applications demanding well defined
performance and repeatability.
Features
• Five 3.3V differential LVPECL output pairs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx input pairs can accept the following differential
levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx inputs
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.1ns (maximum)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
Block Diagram
CLK_EN Pullup
CLK0 Pulldown
nCLK0 Pullup
00
CLK1 Pulldown
nCLK1 Pullup
11
CLK_SEL Pulldown
D
Q
LE
Pin Assignment
Q0 1
20 VCC
nQ0 2 19 CLK_EN
Q1 3
nQ1 4
18 VCC
17 nCLK1
Q2 5 16 CLK1
Q0
nQ2 6
15 VEE
nQ0
Q3 7
14 nCLK0
Q1
nQ3 8
13 CLK0
nQ1
Q4 9 12 CLK_SEL
nQ4 10 11 VCC
Q2
nQ2
85304-01
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
Q4
package body
nQ4
G Package
Top View
© 2015 Integrated Device Technology, Inc
1
Revision E December 2, 2015
Share Link: 