ICS601G-01 Просмотр технического описания (PDF) - Integrated Device Technology
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ICS601G-01 Datasheet PDF : 9 Pages
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ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
CLK 1
REFEN 2
VDD 3
VDD 4
VDD 5
X2 6
S1 7
X1/ICLK 8
16 GND
15 GND
14 GND
13 REFOUT
12 OE
11 S0
10 S3
9 S2
16 Pin (150 mil) TSSOP or SOIC
Pin Descriptions
Multiplier Select Table
S3 S2 S1 S0 CLK (see note 2 on following page)
0000
0001
TEST
TEST
0010
0011
Input x1
Input x3
0100
0101
Input x4
Input x5
0110
0111
Input x6
Input x8
1000
1001
1010
1011
TEST
Crystal osc. pass through (no PLL)
Input x2
TEST
1100
1101
1110
1111
Input x8
Input x10
Input x12
Input x16
0 = connect directly to ground
1 = connect directly to VDD
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14 - 16
Pin
Name
CLK
REFEN
VDD
VDD
VDD
X2
S1
X1/ICLK
S2
S3
S0
OE
REFOUT
GND
Pin
Type
Output
Input
Power
Power
Power
XO
Input
XI
Input
Input
Input
Input
Output
Power
Pin Description
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Leave disconnected for an external clock input.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states both output clocks when low. Internal pull-up.
Buffered crystal oscillator clock output. Controlled by REFIN.
Connect to ground.
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
2
ICS601-01 REV M 102709
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