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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Microchip Technology 

KSZ9031RNX

During the speed transition, the receive clock is stretched on either a positive or negative pulse to ensure that no

clock glitch is presented to the MAC.

• TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These

two RGMII control signals are valid at the falling clock edge.

After power-up or reset, the KSZ9031RNX is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of

the RGMII mode capability options. See the Strap-In Options - KSZ9031RNX section.

The KSZ9031RNX has the option to output a 125 MHz reference clock on the CLK125_NDO pin. This clock provides a

lower-cost reference clock alternative for RGMII MACs that require a 125 MHz crystal or oscillator. The 125 MHz clock

output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.

3.9.1 RGMII SIGNAL DEFINITION

Table 3-3 describes the RGMII signals. Refer to the RGMII Version 2.0 Specification for more detailed information.

TABLE 3-3: RGMII SIGNAL DEFINITION

RGMII Signal

Name (per spec)

RGMII Signal

Name (per

KSZ9031RNX)

Pin Type (with

respect to PHY)

Pin Type (with

respect to MAC)

Description

TXC

TX_CTL

TXD[3:0]

RXC

RX_CTL

RXD[3:0]

GTX_CLK

TX_EN

TXD[3:0]

RX_CLK

RX_DV

RXD[3:0]

Input

Input

Input

Output

Output

Output

Output

Output

Output

Input

Input

Input

Transmit Reference Clock

(125MHz for 1000Mbps, 25MHz for

100Mbps, 2.5MHz for 10Mbps)

Transmit Control

Transmit Data[3:0]

Receive Reference Clock

(125 MHz for 1000 Mbps, 25 MHz

for 100 Mbps, 2.5 MHz for

10 Mbps)

Receive Control

Receive Data[3:0]

3.9.2 RGMII SIGNAL DIAGRAM

The KSZ9031RNX RGMII pin connections to the MAC are shown in Figure 3-4.

FIGURE 3-4:

KSZ9031RNX RGMII INTERFACE

KSZ9031RNX

GTX _CLK

TX _EN

TXD [3:0]

RGMII

ETHERNET MAC

TXC

TX _CTL

TXD [3:0]

RX_CLK

RX _DV

RXD[3:0]

RXC

RX _CTL

RXD[3:0]

 2016 Microchip Technology Inc.

DS00002117C-page 19

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