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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Microchip Technology 

KSZ9031RNX

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-

pensates for the effect of baseline wander and improves the dynamic range. The differential data conversion circuit con-

verts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/

5B decoder. Finally, the NRZ serial data is converted to the RGMII format and provided as the input data to the MAC.

3.1.3 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)

and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The

scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream

using the same sequence as at the transmitter.

3.1.4 10BASE-T TRANSMIT

The 10BASE-T output drivers are incorporated into the 100BASE-TX drivers to allow for transmission with the same

magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with typical amplitude of

2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASE-T/

10BASE-Te signals have harmonic contents that are at least 31 dB below the fundamental frequency when driven by

an all-ones Manchester-encoded signal.

3.1.5 10BASE-T RECEIVE

On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths to prevent

noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks

onto the incoming signal and the KSZ9031RNX decodes a data frame. The receiver clock is maintained active during

idle periods between receiving data frames.

The KSZ9031RNX removes all 7 bytes of the preamble and presents the received frame starting with the SFD (start of

frame delimiter) to the MAC.

Auto-polarity correction is provided for the receiving differential pair to automatically swap and fix the incorrect +/– polar-

ity wiring in the cabling.

3.2 1000BASE-T Transceiver

The 1000BASE-T transceiver is based-on a mixed-signal/digital-signal processing (DSP) architecture, which includes

the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, preci-

sion clock recovery scheme, and power-efficient line drivers.

Figure 3-2 shows a high-level block diagram of a single channel of the 1000BASE-T transceiver for one of the four dif-

ferential pairs.

DS00002117C-page 14

 2016 Microchip Technology Inc.

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