ICL7662 Просмотр технического описания (PDF) - Renesas Electronics
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ICL7662 Datasheet PDF : 11 Pages
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ICL7662
Typical Performance Curves (See Figure 14, Test Circuit) (Continued)
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
10
100
1K
10K
OSCILLATOR FREQUENCY (Hz)
FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
NOTE:
4. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 14). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7662, to the negative side of the load. Ideally,
VOUT 2VIN, IS 2IL, so VIN x IS VOUT x IL.
Circuit Description
The ICL7662 contains all the necessary circuitry to complete a
negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive 10F polarized
electrolytic capacitors. The mode of operation of the device
may be best understood by considering Figure 15, which
shows an idealized negative voltage converter. Capacitor C1 is
charged to a voltage, V+, for the half cycle when switches S1
and S3 are closed. (Note: Switches S2 and S4 are open during
this half cycle.) During the second half cycle of operation,
switches S2 and S4 are closed, with S1 and S3 open, thereby
shifting capacitor C1 negatively by V+ volts. Charge is then
transferred from C1 to C2 such that the voltage on C2 is exactly
V+, assuming ideal switches and no load on C2. The lCL7662
approaches this ideal situation more closely than existing non-
mechanical circuits.
In the lCL7662, the 4 switches of Figure 15 are MOS power
switches; S1 is a P-Channel device and S2, S3 and S4 are N-
Channel devices. The main difficulty with this approach is that
in integrating the switches, the substrates of S3 and S4 must
always remain reverse biased with respect to their sources, but
not so much as to degrade their “ON” resistances. In addition,
at circuit startup, and under output short circuit conditions
(VOUT = V+), the output voltage must be sensed and the
substrate bias adjusted accordingly. Failure to accomplish this
would result in high power losses and probable device latchup.
This problem is eliminated in the ICL7662 by a logic network
which senses the output voltage (VOUT) together with the level
translators, and switches the substrates of S3 and S4 to the
correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral part of
the anti-latchup circuitry, however its inherent voltage drop can
degrade operation at low voltages. Therefore, to improve low
voltage operation the “LV” pin should be connected to
GROUND, disabling the regulator. For supply voltages greater
than 10V the LV terminal must be left open to insure latchup
proof operation, and prevent device damage.
+
C1 -
1
8
2
ICL7662
7
3
6
4
5
COSC
(NOTE)
IS V+
(+5V)
IL
RL
-VOUT
C2 -
10F +
NOTE: For large value of COSC (> 1000pF) the values of C1 and C2
should be increased to 100F.
FIGURE 14. ICL7662 TEST CIRCUIT
FN3181 Rev.4.00
Jan 9, 2006
Page 6 of 11
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