LHF16J04 Просмотр технического описания (PDF) - Sharp Electronics

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LHF16J04

Flash Memory 16M (1M × 16/2M × 8)

Sharp Electronics 

SHARP

LHFl6504

8

2.1 Data Protection

Wkn vccw~vccw,,~ memory contents cannot be

altered. The GUI. with two-step block erase. full chip

erase. word/byte write or lock-bit configuration command

sequences, provides protection from unwanted operations

even when high voltage is applied to Vccw. All write

functions are disabled when Vcc is below the write

lockout voltage VLKO or when RP# is at V,,. The device’s

block locking capability provides additional protection

from inadvertent code or data alteration by gating block

erase, full chip erase and word/byte write operations.

Refer to Table 5 for write protection alternatives.

3 BUS OPERATlON

l3e local CPU reads and writes flash memory in-system.

411 bus cycles to or from the flash memory conform to

standardmicroprocessobruscycles.

3.1 Read

nformation can be read from any block. identifier codes

)r statusregisterindependentof the Vccw voltage. RP#

:anbeat V,,.

i-he first task is to write the appropriate read mode

:ommand(Read Array, Read Identifier Codesor Read

itatusRegister)to the GUI. Upon initial device power-up

jr after exit from reset mode, the device automatically

esetsto readarray mode. Six control pinsdictate thedata

low in and out of the component:CE#. OE#. BYTE#,

JZ#, RP# andWP#. CE# andOE# mustbe driven active

3 obtain data at the outputs.CE# is the device selection

ontrol. and when active enablesthe selectedmemory

evice. OE# is the data output (DQ,-DQlj) control and

{henactive drives the selectedmemorydataonto the l/O

us. BYTE# is the device l/O interface mode control.

VE# must be at V,,, RP# must be at V,,. and BYTE#

nd WP# mustbe at V,, or V,,. Figure 14. 15 illustrates

:ad cycle.

2 Output Disable

v’ith OE# at a logic-high level (VI,), the device outputs

re disabled.Output pins (DQ,-DQ,,) are placed in a

igh-impedancestate.

3.3 Standby

CE# a.t a logic-high level (V,,) places the device ir

standby modewhich substantiallyreducesdevice powel

consumption.DQ,-DQ,, outputs are placed in a high-

impedancestateindependenot f OE#. If deselectedduring

block erase,full chip erase,word/byte write or lock-bil

confi,ouration, the device continues functioning, ant

consumingactive poweruntil theoperationcompletes.

3.4 Reset

RP#at V,, initiatestheresetmode.

In read modes,RP#-low deselectsthe memory. places

output drivers in a high-impedancestateand turns off all

internal circuits.RP# mustbeheld low for a minimumot

IOOns.Time tpHQVis required after return from reset

modeuntil initial memoryaccessoutputsare valid. After

this wake-up interval. normal operation is restored.The

GUI is resetto readarray modeandstatusregisteris setto

80H.

During block erase.full chip erase,word/byte write or

lock-bit configuradon modes.RP#-low will abort the

operation.RY/E%Y#remainslow until the resetoperation

is complete.Memory contentsbeingalteredareno longer

valid; the data may be partially erasedor written. Time

tpmvL is required after RP# goes to logic-high (VIH)

beforeanothercommandcanbewritten.

As with any automateddevice, it is important to assert

RP# during systemreset.When the systemcomesout of

reset,it expectsto readfrom the flashmemory.Automated

flash memoriesprovide statusinformation when accessed

during block erase. full chip erase. word/byte write or

lock-bit configurationmodes.If a CPU resetoccurswith

no flash memoryreset.properCPU initialization may not

occur becausethe flashmemory may be providing status

information instead of array data. SHARP’s flash

memories allow proper CPU initialization following a

system reset through the use of the RP# input. In this

application.RP# is controlledby the sameRESET# signal

that resetsthesystemCPU.

Rev. 1.25

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