CAT25010HU4E-GT3 Просмотр технического описания (PDF) - ON Semiconductor

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CAT25010HU4E-GT3

1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM

ON Semiconductor 

CAT25010, CAT25020, CAT25040

Table 10. STATUS REGISTER

7

6

5

1

1

1

4

3

2

1

0

1

BP1

BP0

WEL

RDY

Table 11. BLOCK PROTECTION BITS

Status Register Bits

BP1

BP0

Array Address Protected

0

0

None

0

1

CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF

1

0

CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF

1

1

CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF

Protection

No Protection

Quarter Array Protection

Half Array Protection

Full Array Protection

WRITE OPERATIONS

The CAT25010/20/40 device powers up into a write

disable state. The device contains a Write Enable Latch

(WEL) which must be set before attempting to write to the

memory array or to the status register. In addition, the

address of the memory location(s) to be written must be

outside the protected area, as defined by BP0 and BP1 bits

from the status register.

Write Enable and Write Disable

The internal Write Enable Latch and the corresponding

Status Register WEL bit are set by sending the WREN

instruction to the CAT25010/20/40. Care must be taken to

take the CS input high after the WREN instruction, as

otherwise the Write Enable Latch will not be properly set.

WREN timing is illustrated in Figure 3. The WREN

instruction must be sent prior to any WRITE or WRSR

instruction.

The internal write enable latch is reset by sending the

WRDI instruction as shown in Figure 4. Disabling write

operations by resetting the WEL bit, will protect the device

against inadvertent writes.

CS

SCK

SI

0 0 0 00 1 10

SO

Dashed Line = mode (1, 1)

HIGH IMPEDANCE

Figure 3. WREN Timing

CS

SCK

SI

SO

Dashed Line = mode (1, 1)

00 0 0 0 1 00

HIGH IMPEDANCE

Figure 4. WRDI Timing

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