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MMA8451QR1

MMA8451Q, 3-axis, 14-bit/8-bit digital accelerometer

NXP Semiconductors. 

2.3

I2C interface characteristics

Table 4. I2C slave timing values(1)

Parameter

Symbol

I2C Fast Mode

Unit

Min

Max

SCL clock frequency

Bus-free time between stop and start condition

(Repeated) start hold time

Repeated start setup time

Stop condition setup time

SDA data-hold time

SDA setup time

SCL clock low time

SCL clock high time

SDA and SCL rise time

SDA and SCL fall time

SDA valid time (4)

SDA valid acknowledge time (5)

Pulse width of spikes on SDA and SCL that must be suppressed by

internal input filter

fSCL

0

400

kHz

tBUF

1.3

—

μs

tHD;STA

0.6

—

μs

tSU;STA

0.6

—

μs

tSU;STO

tHD;DAT

0.6

0.05

—

μs

0.9(2)

μs

tSU;DAT

100

—

ns

tLOW

1.3

—

μs

tHIGH

0.6

—

μs

tr

20 + 0.1 Cb(3)

300

ns

tf

20 + 0.1 Cb(3)

300

ns

tVD;DAT

—

0.9(2)

μs

tVD;ACK

—

0.9(2)

μs

tSP

0

50

ns

Capacitive load for each bus line

Cb

—

400

pF

1.All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels.

2.This device does not stretch the low period (tLOW) of the SCL signal.

3.Cb = total capacitance of one bus line in pF.

4.tVD;DAT = time for data signal from SCL low to SDA output (high or low, depending on which one is worse).

5.tVD;ACK = time for acknowledgement signal from SCL low to SDA output (high or low, depending on which one is worse).

MMA8451Q

8

VIL = 0.3VDD

VIH = 0.7VDD

Figure 5. I2C slave timing diagram

Sensors

NXP Semiconductors N.V.

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