MFRC52201HN1/TRAYBM_10 Просмотр технического описания (PDF) - NXP Semiconductors.

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MFRC52201HN1/TRAYBM_10

Contactless reader IC

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Contactless reader IC

Table 69. RxThresholdReg register (address 18h);

reset value: 84h bit allocation . . . . . . . . . . . . .51

Table 70. RxThresholdReg register bit descriptions . . . .51

Table 71. DemodReg register (address 19h);

reset value: 4Dh bit allocation . . . . . . . . . . . . .51

Table 72. DemodReg register bit descriptions . . . . . . . . .51

Table 73. Reserved register (address 1Ah);

reset value: 00h bit allocation . . . . . . . . . . . . .52

Table 74. Reserved register bit descriptions . . . . . . . . . .52

Table 75. Reserved register (address 1Bh);

reset value: 00h bit allocation . . . . . . . . . . . . .52

Table 76. Reserved register bit descriptions . . . . . . . . . .52

Table 77. MfTxReg register (address 1Ch);

reset value: 62h bit allocation . . . . . . . . . . . . .52

Table 78. MfTxReg register bit descriptions . . . . . . . . . .52

Table 79. MfRxReg register (address 1Dh);

reset value: 00h bit allocation . . . . . . . . . . . . .53

Table 80. MfRxReg register bit descriptions . . . . . . . . . .53

Table 81. Reserved register (address 1Eh);

reset value: 00h bit allocation . . . . . . . . . . . . .53

Table 82. Reserved register bit descriptions . . . . . . . . . .53

Table 83. SerialSpeedReg register (address 1Fh);

reset value: EBh bit allocation . . . . . . . . . . . . .53

Table 84. SerialSpeedReg register bit descriptions . . . . .53

Table 85. Reserved register (address 20h); reset value:

00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .54

Table 86. Reserved register bit descriptions . . . . . . . . . .54

Table 87. CRCResultReg (higher bits) register

(address 21h); reset value: FFh bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 88. CRCResultReg register higher bit descriptions 54

Table 89. CRCResultReg (lower bits) register

(address 22h); reset value: FFh bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 90. CRCResultReg register lower bit descriptions .54

Table 91. Reserved register (address 23h);

reset value: 88h bit allocation . . . . . . . . . . . . .55

Table 92. Reserved register bit descriptions . . . . . . . . . .55

Table 93. ModWidthReg register (address 24h);

reset value: 26h bit allocation . . . . . . . . . . . . .55

Table 94. ModWidthReg register bit descriptions . . . . . .55

Table 95. Reserved register (address 25h);

reset value: 87h bit allocation . . . . . . . . . . . . .55

Table 96. Reserved register bit descriptions . . . . . . . . . .55

Table 97. RFCfgReg register (address 26h);

reset value: 48h bit allocation . . . . . . . . . . . . .56

Table 98. RFCfgReg register bit descriptions . . . . . . . . .56

Table 99. GsNReg register (address 27h);

reset value: 88h bit allocation . . . . . . . . . . . . .56

Table 100. GsNReg register bit descriptions . . . . . . . . . .56

Table 101. CWGsPReg register (address 28h);

reset value: 20h bit allocation . . . . . . . . . . . . . 57

Table 102. CWGsPReg register bit descriptions . . . . . . . 57

Table 103. ModGsPReg register (address 29h);

reset value: 20h bit allocation . . . . . . . . . . . . . 57

Table 104. ModGsPReg register bit descriptions . . . . . . . 57

Table 105. TModeReg register (address 2Ah);

reset value: 00h bit allocation . . . . . . . . . . . . . 57

Table 106. TModeReg register bit descriptions . . . . . . . . 58

Table 107. TPrescalerReg register (address 2Bh);

reset value: 00h bit allocation . . . . . . . . . . . . . 58

Table 108. TPrescalerReg register bit descriptions . . . . . 58

Table 109. TReloadReg (higher bits) register

(address 2Ch); reset value: 00h bit allocation . 59

Table 110. TReloadReg register higher bit descriptions . 59

Table 111. TReloadReg (lower bits) register

(address 2Dh); reset value: 00h bit allocation . 59

Table 112. TReloadReg register lower bit descriptions . . 59

Table 113. TCounterValReg (higher bits) register

(address 2Eh); reset value: xxh bit allocation . 59

Table 114. TCounterValReg register higher bit

descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 115. TCounterValReg (lower bits) register

(address 2Fh); reset value: xxh bit allocation . 59

Table 116. TCounterValReg register lower bit

descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 117. Reserved register (address 30h);

reset value: 00h bit allocation . . . . . . . . . . . . . 60

Table 118. Reserved register bit descriptions . . . . . . . . . 60

Table 119. TestSel1Reg register (address 31h);

reset value: 00h bit allocation . . . . . . . . . . . . . 60

Table 120. TestSel1Reg register bit descriptions . . . . . . . 60

Table 121. TestSel2Reg register (address 32h);

reset value: 00h bit allocation . . . . . . . . . . . . . 60

Table 122. TestSel2Reg register bit descriptions . . . . . . . 61

Table 123. TestPinEnReg register (address 33h);

reset value: 80h bit allocation . . . . . . . . . . . . . 61

Table 124. TestPinEnReg register bit descriptions . . . . . 61

Table 125. TestPinValueReg register (address 34h);

reset value: 00h bit allocation . . . . . . . . . . . . . 61

Table 126. TestPinValueReg register bit descriptions . . . 62

Table 127. TestBusReg register (address 35h);

reset value: xxh bit allocation . . . . . . . . . . . . . 62

Table 128. TestBusReg register bit descriptions . . . . . . . 62

Table 129. AutoTestReg register (address 36h);

reset value: 40h bit allocation . . . . . . . . . . . . . 62

Table 130. AutoTestReg register bit descriptions . . . . . . . 63

Table 131. VersionReg register (address 37h);

reset value: xxh bit allocation . . . . . . . . . . . . . 63

Table 132. VersionReg register bit descriptions . . . . . . . . 63

Table 133. AnalogTestReg register (address 38h);

reset value: 00h bit allocation . . . . . . . . . . . . . 63

continued >>

MFRC522_34

Product data sheet

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All information provided in this document is subject to legal disclaimers.

Rev. 3.4 — 5 March 2010

112134

© NXP B.V. 2010. All rights reserved.

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