EP1C6F240I7N Просмотр технического описания (PDF) - Altera Corporation

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EP1C6F240I7N

Cyclone FPGA Family Data Sheet

Altera Corporation 

Cyclone Device Handbook, Volume 1

Figure 2–1. Cyclone EP1C12 Device Block Diagram

IOEs

Logic Array

PLL

EP1C12 Device

M4K Blocks

The number of M4K RAM blocks, PLLs, rows, and columns vary per

device. Table 2–1 lists the resources available in each Cyclone device.

Table 2–1. Cyclone Device Resources

Device

EP1C3

EP1C4

EP1C6

EP1C12

EP1C20

M4K RAM

Columns

1

1

1

2

2

Blocks

13

17

20

52

64

PLLs

1

2

2

2

2

LAB Columns LAB Rows

24

13

26

17

32

20

48

26

64

32

2–2

Preliminary

Altera Corporation

May 2008

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