EP1C12F240C6N Просмотр технического описания (PDF) - Altera Corporation

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EP1C12F240C6N

Cyclone FPGA Family Data Sheet

Altera Corporation 

Cyclone Device Handbook, Volume 1

performance and flexibility. Each LE can drive 30 other LEs through fast

local and direct link interconnects. Figure 2–3 shows the direct link

connection.

Figure 2–3. Direct Link Connection

Direct link interconnect from

left LAB, M4K memory

block, PLL, or IOE output

Direct link interconnect from

right LAB, M4K memory

block, PLL, or IOE output

Direct link

interconnect

to left

Local

Interconnect

Direct link

interconnect

to right

LAB

2–4

Preliminary

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs.

The control signals include two clocks, two clock enables, two

asynchronous clears, synchronous clear, asynchronous preset/load,

synchronous load, and add/subtract control signals. This gives a

maximum of 10 control signals at a time. Although synchronous load and

clear signals are generally used when implementing counters, they can

also be used with other functions.

Each LAB can use two clocks and two clock enable signals. Each LAB's

clock and clock enable signals are linked. For example, any LE in a

particular LAB using the labclk1 signal will also use labclkena1. If

the LAB uses both the rising and falling edges of a clock, it also uses both

LAB-wide clock signals. Deasserting the clock enable signal will turn off

the LAB-wide clock.

Each LAB can use two asynchronous clear signals and an asynchronous

load/preset signal. The asynchronous load acts as a preset when the

asynchronous load data input is tied high.

Altera Corporation

May 2008

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