VPX3225D Просмотр технического описания (PDF) - Micronas
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VPX3225D Datasheet PDF : 92 Pages
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PRELIMINARY DATA SHEET
VPX 3225D, VPX 3224D
Contents, continued
Page
Section Title
26
2.9.
Operational Modes
26
2.9.1.
Open Mode
26
2.9.2.
Scan Mode
28
2.10.
Windowing the Video Field
29
2.11.
Temporal Decimation
30
2.12.
Data Slicer
30
2.12.1.
Slicer Features
30
2.12.2.
Data Broadcast Systems
31
2.12.3.
Slicer Functions
31
2.12.3.1. Input
31
2.12.3.2. Automatic Adaptation
31
2.12.3.3. Standard Selection
31
2.12.3.4. Output
33
2.13.
VBI Data Acquisition
33
2.13.1.
Raw VBI Data
34
2.13.2.
Sliced VBI Data
35
2.14.
Control Interface
35
2.14.1.
Overview
35
2.14.2.
I2C-Bus Interface
35
2.14.3.
Reset and I2C Device Address Selection
35
2.14.4.
Protocol Description
36
2.14.5.
FP Control and Status Registers
37
2.15.
Initialization of the VPX
37
2.15.1.
Power-on-Reset
37
2.15.2.
Software Reset
37
2.15.3.
Low Power Mode
38
2.16.
JTAG Boundary-Scan, Test Access Port (TAP)
38
2.16.1.
General Description
38
2.16.2.
TAP Architecture
38
2.16.2.1. TAP Controller
38
2.16.2.2. Instruction Register
38
2.16.2.3. Boundary Scan Register
39
2.16.2.4. Bypass Register
39
2.16.2.5. Device Identification Register
39
2.16.2.6. Master Mode Data Register
39
2.16.3.
Exception to IEEE 1149.1
39
2.16.4.
IEEE 1149.1–1990 Spec Adherence
39
2.16.4.1. Instruction Register
39
2.16.4.2. Public Instructions
40
2.16.4.3. Self-Test Operation
40
2.16.4.4. Test Data Registers
40
2.16.4.5. Boundary-Scan Register
40
2.16.4.6. Device Identification Register
40
2.16.4.7. Performance
44
2.17.
Enable/Disable of Output Signals
Micronas
3
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