L9826_05 Просмотр технического описания (PDF) - STMicroelectronics
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L9826_05 Datasheet PDF : 17 Pages
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L9826
3 Electrical Specifications
Table 4.
Symbol
Electrical Characteristcs (continued)
(4.5V ≤ VCC ≤ 5,5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified).
Parameter
Test Condition
Min. Typ.
fclk Clock frequency
50% duty cycle
tclh Minimum time CLK = HIGH
160
tcll Minimum time CLK = LOW
160
tpcld
Propagation delay
CLK to data at SDO valid
4,9V ≤ VCC ≤ 5,1V
tcsdv
NCS = LOW to data at SDO
active
tsclch CLK low before NCS low
Setup time CLK to NCS change
H/L
100
thclcl
CLK change L/H after NCS =
low
100
tscld SDI input setup time
CLK change H/L after SDI data
valid
20
thcld SDI input hold time
SDI data hold after CLK change
H/L
tsclcl CLK low before NCS high
150
thclch CLK high after NCS high
150
tpchdz NCS L/H to output data float
NCS pulse filter time
Multiple of 8 CLK cycles inside
NCS period
Max.
3
100
100
20
100
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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