CL1K100FC256-3 Просмотр технического описания (PDF) - Clear Logic
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CL1K100FC256-3 Datasheet PDF : 16 Pages
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LIBERATOR CL1K100 (PRELIMINARY)
AC Electrical Specifications
I/O Element Timing Parameters [5] Speed: -1
Symbol
Parameter
Min Max
tIOD IOE Register Data Delay
2.4
tIOC IOE Register Control Signal Delay
0.3
tIOCO IOE Register Clock to Output Delay
0.2
tIOCOMB IOE Combinatorial Delay
0.5
tIOSU IOE Register Setup Time Before Clock
2.2
tIOH IOE Register Hold Time After Clock
0.5
tIOCLR IOE Register Clear Delay
0.2
Output Buffer and Pad Delay
tOD1 Slow Slew Rate = off, VCCIO = VCCINT
1.1
tOD2
Output Buffer and Pad Delay
Slow Slew Rate = off, VCCIO = Low Voltage
0.6
tOD3
Output Buffer and Pad Delay
Slow Slew Rate = on
3.0
tZX Output Buffer Disable Delay[6]
1.1
Output Buffer Disable Delay
tZX1
Slow Slew Rate = off, VCCIO = VCCINT[6]
1.1
Output Buffer Disable Delay
tZX2 Slow Slew Rate = off, VCCIO = Low
0.6
Voltage[6]
Output Buffer Disable Delay
tZX3
Slow Slew Rate = on[6]
3.0
tINREG
IOE Input Pad and Buffer to IOE Register
Delay
5.0
tIOFD IOE Register Feedback Delay
3.0
tINCOMB
IOE Input Pad and Buffer to Interconnect
Delay
3.0
Speed: -2
Min Max
2.8
0.3
0.2
0.6
2.6
0.6
0.2
1.3
0.9
3.5
1.3
1.3
0.9
3.5
5.9
3.6
3.6
Speed: -3
Min Max Unit
3.8
ns
0.5
ns
0.3
ns
0.8
ns
3.5
ns
0.8
ns
0.3
ns
1.8
ns
1.6
ns
4.8
ns
1.8
ns
1.6
ns
1.6
ns
4.8
ns
8.0
ns
4.8
ns
4.8
ns
1K tbl 06
Page 9
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