CL1K100FC256-3 Просмотр технического описания (PDF) - Clear Logic

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CL1K100FC256-3

LIBERATOR

Clear Logic 

LIBERATOR CL1K100 (PRELIMINARY)

Description

The LIBERATOR™ CL1K family offers you all of the time-to-

market benefits of designing with programmable logic. Simply

use Altera ACEX® 1K FPGAs to prototype and verify the design.

Then, take five minutes to submit the bitstream using Clear

Logic's web site! Within eight weeks, your system can be in

volume production using compatible Clear Logic devices.

LIBERATOR technology frees you to completely design,

prototype, and verify your custom logic using Altera ACEX 1K

products. Clear Logic's innovative technology eliminates NRE

costs, test vector development, ordering minimums, and long lead

times. No re-simulation or re-layout is required, because Clear

Logic offers an architecture that is exactly compatible to the

functionality of the FPGA prototype. Clear Logic's NoFault® test

technology ensures complete test coverage through the use of

special scan test registers.

The LIBERATOR family is based upon an array of logic

elements. Each logic element contains a configurable look-up

table for combinatorial functions and a register for sequential

operations. Eight logic elements in a group form a block. Logic

functions and signal routing are defined by Clear Logic's

proprietary vertical metal links.

Laser-based configuration allows quick-turn prototyping and

eliminates NRE costs for photomasks. Inherent CL1K family

performance benefits include extremely consistent propagation

delays, reduced power consumption, and improved immunity to

noise and upset events.

Configuration

The "Gate Array" configuration mode eliminates the need for

external EPROMs or software configuration. The LIBERATOR

device is already factory-configured when it is shipped. When

using the device in the "Gate Array" mode, it powers up fully

configured. In this mode, if the customer selects INIT_DONE

option, this pin will always be high.

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