CL1K30FC256-1 Просмотр технического описания (PDF) - Clear Logic
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CL1K30FC256-1 Datasheet PDF : 16 Pages
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LIBERATOR CL1K30 (PRELIMINARY)
AC Electrical Specifications cont.
External Timing Parameters[4]
Symbol
Parameter
Register to Register Delay via Four LEs,
tDRR Three Row Interconnects, and Four Local
Interconnects
tINSU
Setup Time with Global Clock at IOE
Regis ter
tINH Hold time with Global Clock at IOE Register
tOUTCO Output Data Hold Time After Clock
Speed: -1
Min Max
8.0
3.0
0.0
2.0
3.5
Speed: -2
Min Max
9.5
3.6
0.0
2.0
4.5
Speed: -3
Min Max Unit
12.5 ns
4.8
ns
0.0
ns
2.0
7.1
ns
1K tbl 07A
Logic Element Timing Parameters[5]
Speed: -1
Symbol
Parameter
Min Max
tLUT Look-up Table Delay for Data-in
0.6
tCLUT Look-up Table Delay for Carry-in
0.5
tRLUT
Look-up Table Delay for LE Register
Feedback
0.7
tPACKED Data-in to Packed Register Delay
0.5
tEN LE Register Enable Delay
0.6
tCICO Carry-in to Carry-out Delay
0.2
tCGEN Data-in to Carry-out Delay
0.5
tCGENR LE Register Feedback to Carry-out Delay
0.2
tCASC Cascade Chain Routing Ddelay
0.8
tC LE Register Control Signal Delay
0.5
tCO LE Register Clock-to-output Delay
0.5
tCOMB Combinatorial Delay
0.5
tSU LE Register Setup Time Before Clock
0.5
tH LE Register Hold Time After Clock
0.9
tPRE LE Register Preset Delay
0.5
tCLR LE Register Clear Delay
0.5
tCH Clock High Time
2.0
tCL Clock Low Time
2.0
Speed: -2
Min Max
0.8
0.6
0.8
0.6
0.7
0.2
0.5
0.2
0.9
0.6
0.6
0.6
0.6
1.1
0.6
0.6
2.5
2.5
Speed: -3
Min Max Unit
1.1
ns
0.8
ns
1.1
ns
0.8
ns
0.9
ns
0.3
ns
0.8
ns
0.3
ns
1.2
ns
0.8
ns
0.7
ns
0.7
ns
0.8
ns
1.5
ns
0.8
ns
0.8
ns
3.0
ns
3.0
ns
1K tbl 08
Page 10
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