GS9091B Просмотр технического описания (PDF) - Semtech Corporation
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GS9091B Datasheet PDF : 73 Pages
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Table 1-1: Ball List and Description (Continued)
Ball
Name
B9
DVB_ASI
C1, C2
ANA_VDD
C8, E9, F9, H8 IO_VDD
D1, D2
ANA_GND
D4, D5, E4,
E5, F4, F5, G4,
G5
D6, D7, E6,
E7, F6, F7, G6,
G7
CORE_GND
IO_GND
E1
EQ_GND
E2
F1, G1
F2, F3, G2,
G3, H2, H3
TERM
SDI, SDI
HEAT_SINK_GND
H1
EQ_VDD
H9
RD_RESET
J1, K1
AGC+, AGC-
J2
EQ_BYPASS
Timing
Type Description
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
This pin and its function are only supported in Manual mode
(AUTO/MAN = LOW).
When the application layer sets this pin HIGH, the device will be
configured to operate in DVB-ASI mode. The SMPTE_BYPASS pin
will be ignored.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
Analog
Input
Power
Power supply connection for analog core. Connect to +3.3V DC.
Non
Input
Synchronous Power
Power supply for digital I/O.
For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V
DC.
For a 5V tolerant I/O, connect pins to a +3.3V DC.
Analog
Input
Power
Ground connection for analog core. Connect to GND.
Non
Input
Synchronous Power
Ground connection for digital logic blocks. Connect to GND.
Non
Input
Synchronous Power
Ground connection for digital I/O. Connect to GND.
Analog
Analog
Analog
Analog
Analog
Input
Power
Input
Input
Input
Power
Input
Power
Synchronous
with RD_CLK
Input
Analog
Input
Analog
Input
Ground connection for equalizer core. Connect to GND.
Termination for serial digital input. AC couple to ANA_GND
Serial digital differential input pair.
Heat sink connection. Connect to main ground plane of application
board.
Power supply connection for equalizer core. Connect to +3.3V DC.
FIFO READ RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH and DVB-ASI = LOW), and the internal FIFO is configured
for video mode (Section 3.10.1).
A HIGH to LOW transition will reset the FIFO pointer to address
zero of the memory.
External AGC capacitor connection. Connect J1 and K1 together
through a 1uF capacitor.
CONTOL SIGNAL INPUT
Signal levels are 3.3V CMOS / LVTTL compatible.
Equalizer bypass.
When EQ_BYPASS is HIGH, the equalizer stages are bypassed.
When EQ_BYPASS is LOW, normal operation of the equalizer stages
resumes.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
8 of 73
Proprietary & Confidential
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