EVAL-AD9834EB Просмотр технического описания (PDF) - Analog Devices
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EVAL-AD9834EB Datasheet PDF : 20 Pages
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PRELIMINARY TECHNICAL DATA
AD9834
100nF
10nF
RSET
6.8 K
CAP/2.5V
REGULATOR
REFOUT
ON-BOARD
REFERENCE
FS
ADJUST
FULL-SCALE COMP
CONTROL
AVDD
10nF
12
SIN
ROM
IOUT
10-BIT DAC
AD9834
200R
20pF
Figure 1. Test Circuit With which Specifications are tested.
TIMING CHARACTERISTICS1 (VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Parameter Limit at TMIN to TMAX
t1
20
t2
8
t3
8
t4
25
t5
10
t6
10
t7
5
t8
10
t4 - 5
t9
5
t10
3
t11
8
t11A*
8
1 Guaranteed by design, not production tested.
*See Pin Description Section.
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
Test Conditions/Comments
MCLK Period
MCLK High Duration
MCLK Low Duration
SCLK Period
SCLK High Duration
SCLK Low Duration
FSYNC to SCLK Falling Edge Setup Time
FSYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
FSELECT, PSELECT Setup Time Before MCLK Rising Edge
FSELECT, PSELECT Setup Time After MCLK Rising Edge
MCLK
t1
t2
t3
Figure 2. Master Clock
MCLK
FSEL ECT,
PSEL ECT
VALID DATA
t 11
VALID DATA
t11A
VALID DATA
Figure 3. Control Timing
SCLK
FSYNC
SDATA
t5
t4
t7
t6
t8
D15
D14
t10
t9
D2
D1
D0
D15
D14
Figure 4. Serial Timing
REV PrM
–3–
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