SK2111 Просмотр технического описания (PDF) - Semtech Corporation
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SK2111 Datasheet PDF : 6 Pages
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SK2111
1:10 Differential LVDS Clock Driver
TEST AND MEASUREMENT PRODUCTS
Description
Features
SK2111 is a 1 to 10 data/clock distributor utilizing
LVDS (Low Voltage Differential Signaling) technology
for high speed operation. Data paths are fully differ-
ential from input-to-output for low noise generation
and low pulse width distortion. The design allows
connection of 1 input to all 10 outputs. LVDS I/O
enable high speed data transmission for point-to-point
interconnects. This device can be used as a high
speed differential 1 to 10 signal distribution / fanout
replacing multi-drop bus applications for higher speed
links with improved signal quality. It can also be
used for clock distribution up to 800 MHz.
The SK2111 accepts LVDS signal levels, LVPECL lev-
els directly or PECL with attenuation network resis-
tors. The inputs of SK2111 have an on-chip 100 Ω
termination resistors to minimize the component count.
The OE input is synchronous so that the outputs will
only be enabled/disabled when they are already in the
low state. This feature prevents generating any runt
clocks. The EDQUAD LQFP package has an exposed
heatslug which is connected to VEE substrate.
Supply Voltage Range: +3.0V to +3.6V
Part-to-part skew 75 ps (Max.)
Output channel-to-channel skew is 60 ps (Max.)
800 MHz minimum toggle frequency
Differential output voltage (DVOUT) is 350 mV
(typical) with 100 Ω termination load
LVDS receiver inputs accept LVPECL signals
On-chip 100 Ω input termination resistor
Fast propagation delay of 500 ps (typical)
Receiver input threshold <±100 mV
VREF for LVDS single-ended input applications
ESD Protection of >4000V
Industrial Temperature Range: -40oC to +85oC
Available in Thermally Enhanced EDQUAD
32 Pin LQFP Package
Conforms to ANSI/TIA/EIA-644 LVDS standard
Pin Description
Functional Block Diagram
CLK1
100 Ω
CLK1*
OE
10
Q0:Q9
Q0*:Q9*
LEN Q
D
VREF
1.2V
VCC
Q2*
Q2
Q1*
Q1
Q0*
Q0
VCC
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
SK2111
12
30
11
31
10
32
9
12 34 56 7 8
VCC
Q7
Q7*
Q8
Q8*
Q9
Q9*
VCC
Pin Names
Pin
CLK1, CLK1*
Q0, Q9, Q0*, Q9*
VREF
OE
Function
Differential LVDS Input Pair
Differential LVDS Outputs
LVDS Reference Voltage 1.2V
Output Enable Input LVTTL / LVCMOS
Revision 3 / April 24, 2003
OE
Q0-Q9
0
LOW
1
Qn
Q0*-Q9*
HIGH
Qn*
Truth Table
1
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