FM24CL64B-DG Просмотр технического описания (PDF) - Ramtron International Corporation
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FM24CL64B-DG Datasheet PDF : 13 Pages
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FM24CL64B
Counter
Address
Latch
1,024 x 64
FRAM Array
8
SDA
SCL
WP
A0-A2
Serial to Parallel
Converter
Control Logic
Data Latch
Figure 1. FM24CL64B Block Diagram
Pin Description
Pin Name
A0-A2
Type
Input
SDA
I/O
SCL
WP
VDD
VSS
Input
Input
Supply
Supply
Pin Description
Address 0-2. These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
Serial Data Address. This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of
the part on the falling edge, and in on the rising edge. The SCL input also
incorporates a Schmitt trigger input for noise immunity.
Write Protect. When WP is high, addresses in the entire memory map will be write-
protected. When WP is low, all addresses may be written. This pin is pulled down
internally.
Supply Voltage: 2.7V to 3.6V
Ground
Rev. 3.0
Jan. 2012
Page 2 of 13
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