FM24CL64B(2011) Просмотр технического описания (PDF) - Ramtron International Corporation

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производитель

FM24CL64B
(Rev.:2011)

64Kb Serial 3V F-RAM Memory

Ramtron International Corporation 

FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)

To perform a selective read, the bus master sends out

the slave address with the LSB set to 0. This specifies

a write operation. According to the write protocol,

the bus master then sends the address bytes that are

loaded into the internal address latch. After the

FM24CL64B acknowledges the address, the bus

master issues a start condition. This simultaneously

aborts the write operation and allows the read

command to be issued with the slave address LSB set

to a „1‟. The operation is now a current address read.

By Master

Start

Address

S

Slave Address 1 A

No

Acknowledge

Data Byte

1P

Stop

By F-RAM

Acknowledge Data

Figure 7. Current Address Read

By Master

Start

Address

S

Slave Address 1 A

Acknowledge

No

Acknowledge

Data Byte

A

Data Byte

1P

Stop

By F-RAM

Acknowledge

Data

Figure 8. Sequential Read

Start

By Master

Address

S

Slave Address 0 A

Address MSB

A

Address LSB

Start

Address

AS

Slave Address 1 A

By F-RAM

Acknowledge

Figure 9. Selective (Random) Read

No

Acknowledge

Stop

Data Byte

1P

Data

Rev. 1.1

June 2011

Page 7 of 12

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