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ADMC328

28-Lead ROM-Based DSP Motor Controller with Current Sense

Analog Devices 

ADMC328

Serial Port

The ADMC328 incorporates a complete synchronous serial

port (SPORT1) for serial communication and multiprocessor

communication. The following is a brief list of capabilities of the

ADMC328 SPORT1. Refer to the ADSP-2100 Family User’s

Manual, Third Edition, for further details.

• SPORT1 is bidirectional and has a separate, double-buffered

transmit and receive section.

• SPORT1 can use an external serial clock or generate its own

serial clock internally.

• SPORT1 has independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame synchronization signals are active high or inverted,

with either of two pulsewidths and timings.

• SPORT1 supports serial data word lengths from 3 bits to 16

bits and provides optional A-law and µ-law companding ac-

cording to ITU (formerly CCITT) recommendation G.711.

• SPORT1 receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORT1 can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1), and the Flag In and Flag Out signals.

The internally generated serial clock may still be used in this

configuration.

INTERRUPT OVERVIEW

The ADMC328 can respond to 16 different interrupt sources

with minimal overhead, five of which are internal DSP core

interrupts and 11 are from the motor control peripherals. The five

DSP core interrupts are SPORT1 receive (or IRQ0) and trans-

mit (or IRQ1), the internal timer, and two software interrupts.

The motor control peripheral interrupts are the nine program-

mable I/Os and two from the PWM (PWMSYNC pulse and

PWMTRIP). All motor control interrupts are multiplexed into the

DSP core through the peripheral IRQ2 interrupt. The interrupts

are internally prioritized and individually maskable. A detailed

description of the entire interrupt system of the ADMC328 is

presented later, following a more detailed description of each

peripheral block.

Memory Map

The ADMC328 has two distinct memory types: program memory

and data memory. In general, program memory contains user

code and coefficients, while the data memory is used to store

variables and data during program execution. Both program

memory RAM and ROM are provided on the ADMC328. Pro-

gram memory RAM is arranged as one contiguous 512 × 24-bit

block, starting at address 0x0000. Program memory ROM is a

4K × 24-bit block located at address 0x0800. Data memory is

arranged as a 512 × 16-bit block starting at address 0x3800. The

motor control peripherals are memory mapped into a region of

the data memory space starting at 0x2000. The complete program

and data memory maps are given in Tables II and III, respectively.

Table II. Program Memory Map

• SPORT1 has two data receive pins (DR1A and DR1B), which

are internally multiplexed onto the one DR1 port of the

SPORT1. The particular data receive pin selected is deter-

mined by a bit in the MODECTRL register.

PIN FUNCTION DESCRIPTION

The ADMC328 is available in a 28-lead SOIC package and a

28-lead PDIP package. Table I describes the pins.

Table I. Pin List

Group

Name

# of Input/

Pins Output Function

RESET

SPORT11

1I

6 I/O

CLKOUT1

1O

CLKIN, XTAL 2 I, O

PIO0–PIO81

9 I/O

AUX0–AUX11 2 O

AH–CL

PWMTRIP

6O

1I

V1–V2

2I

VAUX0–VAUX2 3 I

ISENSE

ICONST

1I

1O

VDD

1

GND

1

Processor Reset Input

Serial Port 1 Pins (TFS1,

RFS1, DT1, DR1A, DR1B,

SCLK1)

Processor Clock Output

External Clock or Quartz

Crystal Connection Point

Digital I/O Port Pins

Auxiliary PWM Outputs

PWM Outputs

PWM Trip Signal

Analog Inputs

Auxiliary Analog Input

Current Sense Amplifier Input

ADC Constant Current Source

Power Supply

Ground

Address Range

0x0000–0x002F

0x0030–0x01FF

0x0200–0x07FF

0x0800–0x17FF

0x1800–0x3FFF

Memory

Type Function

RAM

RAM

ROM

Interrupt Vector Table

User Program Memory

Reserved

User Program Memory

Reserved

Table III. Data Memory Map

Address Range

0x0000–0x1FFF

0x2000–0x20FF

0x2100–0x37FF

0x3800–0x39FF

0x3A00–0x3BFF

0x3C00–0x3FFF

Memory

Type

RAM

RAM

Function

Reserved

Memory Mapped Registers

Reserved

User Data Memory

Reserved

Memory Mapped Registers

NOTE

1Multiplexed pins, selectable individually through the PIOSEL ECT and

PIODATA1 registers.

REV. B

–9–

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