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SI533_07 Просмотр технического описания (PDF) - Silicon Laboratories

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SI533_07 Datasheet PDF : 12 Pages
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Si533
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Temp stability = ±7 ppm
±20 ppm
Total Stability
Temp stability = ±20 ppm
±31.5 ppm
Temp stability = ±50 ppm
±61.5 ppm
Powerup Time4
tOSC
10
ms
Settling Time After FS Change tFRQ
10
ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
VDD – 1.25 V
VOD
swing (diff)
1.1
1.9
VPP
LVDS Output Option2
VSE
swing (single-ended)
0.55
0.95
VPP
VO
mid-level
1.125
1.20
1.275
V
VOD
CML Output Option2
VO
swing (diff)
mid-level
0.5
0.7
0.9
VPP
VDD – 0.75
V
VOD
CMOS Output Option3
VOH
VOL
swing (diff)
IOH = 32 mA
IOL = 32 mA
0.70
0.8 x VDD
0.95
1.20
VPP
VDD
V
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
350
ps
CMOS with CL = 15 pF
1
ns
Symmetry (duty cycle)
SYM LVPECL: VDD – 1.3 V (diff)
LVDS: 1.25 V (diff)
45
55
%
CMOS: VDD/2
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Rev. 1.1
3

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