FH8065403552901SR3GU Просмотр технического описания (PDF) - Intel
Номер в каталоге
Компоненты Описание
производитель
FH8065403552901SR3GU Datasheet PDF : 745 Pages
| |||
C2000 Product Family—Contents
14.10.7 Memory Latency Tolerance ...................................................................276
14.11 Security Features.............................................................................................277
14.11.1 Security Features ................................................................................277
14.12 USB 2.0 Based Debug Port ................................................................................277
14.12.1 Theory of Operation.............................................................................278
14.12.1.1 OUT Transactions................................................................279
14.12.1.2 IN Transactions ..................................................................280
14.12.1.3 Debug Software..................................................................281
14.13 USB Over-Current Protection .............................................................................283
14.14 Register Map ...................................................................................................283
14.14.1 PCI Configuration and Capabilities .........................................................284
14.14.2 MMIO Registers...................................................................................285
15 SMBus 2.0 Unit 1 - Host ......................................................................................... 286
15.1 Signal Descriptions ..........................................................................................287
15.2 Features .........................................................................................................287
15.3 Architectural Overview .....................................................................................288
15.4 Controller Characteristics and Operation .............................................................290
15.4.1 Electrical ............................................................................................290
15.4.2 SMBus Behavior on PCIe Reset..............................................................290
15.4.3 Addressing and Configuration................................................................290
15.4.3.1
15.4.3.2
15.4.3.3
ARP Nomenclature ..............................................................291
Unique Device Identifier (UDID) Format .................................292
ARP Slave Behavior.............................................................293
15.4.3.4 ARP Master Behavior ...........................................................299
15.4.3.5 ARP Initialization Flow .........................................................302
15.4.4 SMT System Usage Models ...................................................................304
15.4.5 SMT Security Requirements ..................................................................304
15.4.6 SMT Timing Modes ..............................................................................304
15.4.7 SMT as Master ....................................................................................305
15.4.7.1
15.4.7.2
15.4.7.3
15.4.7.4
15.4.7.5
15.4.7.6
15.4.7.7
Hardware Buffering for Master Support ..................................305
Master Descriptor ...............................................................306
Master Descriptor Usage ......................................................310
Master Transactions Flow .....................................................314
Clearing of Start Bit ............................................................317
Master Retry Flow ...............................................................318
Write Disabling to DIMM SPD EEPROM Addresses ....................319
15.4.8 SMT as Target.....................................................................................319
15.4.8.1
15.4.8.2
15.4.8.3
15.4.8.4
15.4.8.5
Hardware Buffering for Target Support ..................................319
Target Descriptor................................................................320
Target Transaction Status ....................................................323
Target Memory Buffer Hardware-Firmware Flow ......................327
Target Flow........................................................................330
15.4.9 Dynamic SMT Policy Update ..................................................................339
15.4.9.1 Master Policy......................................................................339
15.4.9.2 Target Policy ......................................................................339
15.5 Interrupts .......................................................................................................341
15.5.1 Master Interrupts ................................................................................342
15.5.2 Target Interrupts.................................................................................343
15.5.3 Error Interrupts...................................................................................344
15.5.4 Interrupt Cause Logging.......................................................................345
15.6 SMT RAS Architecture.......................................................................................346
15.6.1 Soft Reset (DEVCTL.IFLR and GCTRL.SRST) ............................................346
15.6.2 Target Reset (GCTRL.TRST) ..................................................................347
15.7 MCTP Over SMBus Packet Header Format ............................................................348
15.8 Register Maps .................................................................................................350
15.8.1 Registers in Configuration Space ...........................................................351
Intel® Atom™ Processor C2000 Product Family for Microserver
Datasheet
10
January 2016
Order Number: 330061-003US
Share Link: 