5L35023 Просмотр технического описания (PDF) - Integrated Device Technology
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5L35023 Datasheet PDF : 38 Pages
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5L35023 Datasheet
Table 7. Electrical Characteristics – Input Parameters
Symbol
VIH
VIL
VIH
VIL
VSWING
IIL
IIH
dTIN
CIN
RPDR
ROUT
Parameter
Conditions
Input High Voltage
Input Low Voltage
Input High Voltage–SEL_DFC
Single-ended inputs–OE pins.
Single-ended inputs–OE pins.
Single-ended latched input.
Input Low Voltage–SEL_DFC
Single-ended latched input.
Input Amplitude–CLKIN
Single-ended input swing.
Input Leakage Low Current
Input Leakage High Current
Input Duty Cycle
Input Capacitance (CLKIN,
CLKINB, OE, SDA, SCL, DFC1:0).
VIN = GND
VIN = 1.89V.
Measurement from differential
waveform.
Pull-down Resistor–OE pin
LVCMOS Output Driver
Impedance (VDDSE = 1.8V)
Minimum
0.65 x VDDSE
GND - 0.3
0.65 x VDDSE
GND - 0.3
600
-20
-20
Typical
Maximum
VDDSE + 0.3
0.35 x VDDSE
VDDSE + 0.3
0.35 x VDDSE
VDD
20
20
Units
V
V
V
V
mV
μA
μA
45
55
%
3
7
pF
550
kΩ
17
Ω
Table 8. Electrical Characteristics – LVCMOS
Symbol
VOH
VOL
IOZDD
tR/F
tODC
Parameter
Output High Voltage
Output Low Voltage
Output Leakage Current
Output Rise/Fall Time
Output Duty Cycle
Output Duty Cycle–REF
Conditions
IOH = -8mA.
IOL = 8mA.
Tri-state outputs, VDDSE = 1.89V.
Single-ended LVCMOS output clock
rise and fall time, 20% to 80% of
VDDSE 1.8V.
LVCMOS (measured at VDDO/2).
Reference clock output or SE1–3 fan
out clock measured at VDDO/2.
Minimum
0.7 x VDDSE
45
40
Typical
1.0
Maximum
VDDSE
0.25 x VDDSE
3
Units
V
V
μA
ns
55
%
60
%
Table 9. Electrical Characteristics – LPHCSL Differential Outputs
Symbol
dV/dt
ΔdV/dt
VMAX
VMIN
VSWING
Parameter
Slew Rate
Slew Rate Mismatch
Maximum Voltage
Minimum Voltage
Voltage Swing
Minimum
1
Typical
2.5
-150
0
-300
300
Maximum
4
20
1150
Units
V/ns
%
mV
mV
mV
Notes
1,2,3,8
1,2,3,8,9
1,6
1,6
1,2,6
©2017 Integrated Device Technology, Inc.
7
July 13, 2017
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