(4) TIMING DIAGRAMS
Read cycle
A0~16
S1
S2
OE
DQ1~8
W = "H" level
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(Note 3)
(Note 3)
(Note 3)
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
(Note 3)
Write cycle (W control mode)
tCW
A0~16
S1
S2
OE
W
DQ1~8
5
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten (W)
ten(OE)
DATA IN
STABLE
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
(Note 3)
(Note 3)