ISP1583 Просмотр технического описания (PDF) - NXP Semiconductors.

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ISP1583

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

Table 3. Pin description …continued

Symbol[1] Pin

Type[2] Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

MODE1 34

J10

G8

I

mode selection input 1; used in split bus mode only:

• LOW: ALE function (address latch enable)

• HIGH (connect to VCC(I/O)): A0 function (address/data

indicator)

Remark: When operating in generic processor mode, set

pin MODE1 as HIGH.

input pad; TTL; 5 V tolerant

DGND

35

H9

F8

-

digital ground

ALE/A0 36

H10

F7

I

Address latch enable input — When pin MODE1 = LOW

during power-up, a falling edge on this pin latches the

address on the multiplexed address and data bus AD[7:0].

Address and data selection input — When pin

MODE1 = HIGH during power-up, the function is

determined by the level on this pin (detected on the rising

edge of the WR_N pulse):

• HIGH: bus AD[7:0] is a register address

• LOW: bus AD[7:0] is register data; used in split bus

mode only

Remark: When operating in generic processor mode with

pin MODE1 = HIGH, this pin must be pulled down using a

10 kΩ resistor.

input pad; TTL; 5 V tolerant

DATA0

37

G9

F6

I/O bit 0 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA1

38

G10

E6

I/O bit 1 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA2

39

F9

E7

I/O bit 2 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA3

40

F10

E8

I/O bit 3 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

VCC(I/O)[4] 41

DATA4

42

E9

D7

E10

D6

-

I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16

I/O bit 4 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA5

43

D10

D8

I/O bit 5 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA6

44

D9

D5

I/O bit 6 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA7

45

C10

D4

I/O bit 7 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA8

46

C9

C8

I/O bit 8 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

DATA9

47

B10

C7

I/O bit 9 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

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