KE5BCCA9M Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5BCCA9M

high-performance Content Addressable Memory (CAM)

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

9M Classification CAM

PRELIMINARY

Kawasaki’s KE5BCCA9M has the following components:

• I/O Port Control

I/O port to input search key data and read/write data. I/O port data bus can be configured as a

72-bit or 40-bit wide bus.

• Pipeline Execution Control

Controls operation with pipeline through the CNTL [15:0].

• Control/Status Register

Defines CAM functions.

• Mask Registers

18 Global Mask Registers in total: 16 72-bit wide user-definable registers and 2 fixed registers

(ALL 0 and ALL 1) for search and write operations.

• Search Logic/Control Logic

Controls CAM functions.

• CAM

72-bit x 128k CAM data table partitioned into 8 banks. Each of which can be configured as

ternary or binary and in table width of 72-bit, 144-bit, 288-bit, or 576-bit. The search operations

can be performed simultaneously on multiple banks. By way of these features, various kinds of

data for Layer-2, 3 and 4 can be stored in one device and managed in different ways.

• Output Port Control

Controls output port, which outputs search results. The DAT data bypass function is provided

for the external SRAM access through this CAM device.

• Flag Logic

Controls the flag status (e.g. Full and Hit). Interfaces with other devices in a cascaded system.

When the CAM table is divided into multiple blocks, the status of the searched block is output.

Version 1.2.0

3

Confidential

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