KE5BCCA9M Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS
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KE5BCCA9M Datasheet PDF : 19 Pages
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Kawasaki LSI
9M Classification CAM
PRELIMINARY
1. Features
Kawasaki’s KE5BCCA9M is a high-performance Content Addressable Memory (CAM). The
following features enable high-speed and high-density “ switching," “ address filtering,” and "packet
classification" applications required for internetworking switching and routing:
• Density: 9.4Mbits Ternary or Binary
• Configurable table Size:
72-bit x 128K, 144-bit x 64K, 288-bit x 32K, or 576-bit x 16K(Ternary or Binary)
• Mixed table size configuration:
Selected by each bank (8banks). Each bank can be individually configured as a 72-bit x 16K,
144-bit x 8K, 288-bit x 4K, or 576-bit x 2K(Ternary or Binary) table.
• Input Clock rate: 83MHz/100MHz/125MHz clock (CLK)
• High-speed search and deterministic latency:
-125: Sustained 125MLPS, (maximum key data width T.B.D.), (latency T.B.D.)
-100: Sustained 100MLPS, 10ns per 144-bit maximum, (latency T.B.D.)
- 83: Sustained 83MLPS, 12ns per 144-bit maximum, 3 cycles latency
• Dual-port architecture
• 72-bit I/O Port Data Bus:
144-bit per 8(T.B.D.)/10/12ns write-in throughput is possible. 72-bit I/O port data bus is also
configurable as a 40-bit wide bus.
• 24-bit Output Port: Search results are output
• Multi-hit support (Highest Hit Address output)
• 18 x 72-bit Global MASK Registers
• Weighted Search without data sorting
• Effective Command Set for Table Management:
- Purge (Invalidate) all the hit entries in one Cycle
- Automatic Learning
• Cascading:
Up to 8pcs --- Glueless without degradation in performance --- 72-bit x 512k table
Cascadable up to 32pcs --- Maximum 72-bit x 2M table
• External SRAM direct connection (Address bypass to SRAM)
• Space-saving package: 324-pin BGA (27mm x 27mm)
• Power supply: 1.2V (core), 2.5V or 1.8V(I/O) --- Selectable I/O voltage (T.B.D.)
Version 1.2.0
1
Confidential
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