ML7041 Просмотр технического описания (PDF) - Unspecified
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ML7041 Datasheet PDF : 28 Pages
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FEDL7041-05
ML7041
TIMING DIAGRAM
Transmit Side PCM Timing (Normal Synchronous Interface)
BCLK
SYNC
PCMOUT
0
1
2
3
4
5
6
7
tSB
tWS
tXD1
tXD2
MSB
tSDX
When tSB >= 0, the Delay of the MSB is defined as tXD1.
When tSB < 0, the Delay of the MSB is defined as tSDX.
Transmit Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0
1
2
3
4
5
6
7
tSB
tBS
SYNC
tWS
tXD1
tXD2
PCMOUT
MSB
8
9
10
tXD3
LSB
8
9
10
tXD3
LSB
Receive Side PCM Timing (Normal Synchronous Interface)
BCLK
0
1
2
3
4
5
6
7
8
9
10
tSB
tWS
SYNC
tDS
tDH
PCMIN
MSB
LSB
Receive Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0
1
2
3
4
5
6
7
8
9
10
tSB
tBS
SYNC
tWS
tDS
tDH
PCMIN
MSB
LSB
Figure 6 PCM Interface Timing
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