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MPC9446FA

3.3V AND 2.5V, LVCMOS CLOCK FANOUT BUFFER

Integrated Device Technology 

MPC9446

3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER

Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VIH

VIL

VOH

VOL

ZOUT

IIN

ICCQ(3)

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Output Impedance

Input Current(2)

Maximum Quiescent Supply Current

1.7

–0.3

1.8

17 – 20(2)

VCC + 0.3

0.7

0.6

±200

2.0

V LVCMOS

V LVCMOS

V IOH = –15 mA(1)

V IOL = 15 mA

Ω

µA VIN = GND or VIN = VCC

mA All VCC Pins

1. The MPC9446 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per

output.

2. Input pull-up / pull-down resistors influence input current.

3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1)

Symbol

Characteristics

Min

fref Input Frequency

0

fMAX Maximum Output Frequency

÷1 output

0

÷2 output

0

Typ

Max

Unit

Condition

250(2)

MHz

250(2)

125

MHz FSELx = 0

MHz FSELx = 1

tP, REF Reference Input Pulse Width

1.4

tr, tf CCLK Input Rise/Fall Time

tPLH Propagation Delay

tPHL

CCLK0,1 to any Q

2.6

CCLK0,1 to any Q

2.6

tPLZ, HZ Output Disable Time

tPZL, LZ Output Enable Time

tsk(O)

Output-to-Output Skew

Within one bank

Any output bank, same output divider

Any output, Any output divider

1.0(3)

5.6

5.5

10

10

150

200

350

ns

ns 0.7 to 1.7 V

ns

ns

ns

ns

ps

ps

ps

tsk(PP)

tSK(P)

Device-to-Device Skew

Output Pulse Skew(4)

3.0

ns

200

ps

DCQ Output Duty Cycle

÷1 or ÷2 output

45

50

55

% DCREF = 50%

tr, tf Output Rise/Fall Time

0.1

1.0

ns 0.6 to 1.8 V

1. AC characteristics apply for parallel output termination of 50 Ω to VTT.

2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.

3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input

pulse width, output duty cycle and maximum frequency specifications.

4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency

dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.

Table 10. AC Characteristics (VCC = 3.3 V + 5%, VCCA, VCCB, VCCC = 2.5 V + 5% or 3.3 V + 5%, TA = –40°C to +85°C)(1) (2)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

tsk(O)

Output-to-Output Skew

Within one bank

Any output bank, same output divider

Any output, Any output divider

150

ps

250

ps

350

ps

tsk(PP)

tPLH,HL

tSK(P)

Device-to-Device Skew

Propagation Delay

Output Pulse Skew(3)

CCLK0,1 to any Q

2.5

ns

See 3.3 V Table

250

ps

DCQ Output Duty Cycle

÷1 or ÷2 output

45

50

55

% DCREF = 50%

1. AC characteristics apply for parallel output termination of 50 Ω to VTT.

2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank.

3. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency

dependent: DCQ = (0.5 ± tSK(P) • fOUT).

IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER

5MPC9446 REV 4 NOVEMBER 28, 2007)

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