H8/3008 Просмотр технического описания (PDF) - Renesas Electronics

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H8/3008

Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Renesas Electronics 

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9.4.5 Operation with 267

Cascaded Connection

Compare Match Count

Mode

9.7.1 Contention

272

between 8TCNT Write

and Clear

Figure 9.18 Contention

between 8TCNT Write

and Clear

Revision (See Manual for Details)

Description amended

• Channels 0 and 1:

When bits CKS2 to CKS0 are set to (100) in 8TCR1,

8TCNT1 counts channel 0 compare match A events.

Channels 0 and 1 are controlled independently.

CMF flag setting, interrupt generation, TMO pin output,

counter clearing, and so on, is in accordance with the

settings for each channel.

Note: When bit ICE = 1 in 8TCSR1, the compare match

register function of TCORB0 in channel 0 cannot be

used.

• Channels 2 and 3:

When bits CKS2 to CKS0 are set to (100) in 8TCR3,

8TCNT3 counts channel 2 compare match A events.

Channels 2 and 3 are controlled independently.

CMF flag setting, interrupt generation, TMO pin output,

counter clearing, and so on, is in accordance with the

settings for each channel.

Note: When bit ICE = 1 in 8TCSR3, the compare match

register function of TCORB2 in channel 2 cannot be

used.

Figure amended

8TCNT write cycle

T1

T2

T3

φ

Address bus

8TCNT address

Internal write signal

Counter clear signal

8TCNT

N

H'00

Rev.4.00 Aug. 20, 2007 page x of xliv

REJ09B0395-0400

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