UT62256CLS-35LLE Просмотр технического описания (PDF) - Utron Technology Inc
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UT62256CLS-35LLE Datasheet PDF : 12 Pages
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Rev. 1.0
UTRON
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 2uA (typ.) L-version
1uA (typ.) LL-version
Single 5V power supply
Extended temperature : -20℃~80℃
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The UT62256C(E) is a 262,144-bit low power
CMOS static random access memory organized
as 32,768 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT62256C(E) is designed for high-speed and
low power application. It is particularly well
suited for battery back-up nonvolatile memory
application.
The UT62256C(E) operates from a single 5V
power supply and all inputs and outputs are fully
TTL compatible
PIN CONFIGURATION
A3
A14
1
28
Vcc
A4
A5
.
A6
ROW
A7
. DECODER
A8
.
A12
A13
A14
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORY ARRAY
512 ROWS × 512 COLUMNS
. ..
COLUMN I/O
COLUMN DECODER
VCC
VSS
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O1
11
I/O2
12
I/O3
13
Vss
14
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
PDIP/SOP
CE
LOGIC
WE CONTROL
OE
A11 A10 A9 A2 A1 A0
OE
1
A11
2
A9
3
A8
4
28
A10
27
CE
26
I/O8
25
I/O7
PIN DESCRIPTION
A13
5
WE
6
24
I/O6
23
I/O5
SYMBOL
DESCRIPTION
Vcc
7
22
I/O4
A14
8
UT62256C
21
Vss
A0 - A14
I/O1 - I/O8
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
A12
9
A7
10
A6
11
A5
12
20
I/O3
19
I/O2
18
I/O1
17
A0
WE
Write Enable Input
OE
Output Enable Input
A4
13
A3
14
16
A1
15
A2
VCC
Power Supply
VSS
Ground
STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
P80071
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