HI-8588CDI Просмотр технического описания (PDF) - Holt Integrated Circuits
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HI-8588CDI Datasheet PDF : 6 Pages
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HI-8588-10
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 35KW of resis-
tance of which 25KW is internal to the chip. The series re-
sistance is connected to level translators whose resistance
to Ground is typically 10KW. In order for the voltage trans-
lation not to be adversely affected, an external 10KW series
resister must be added to each ARINC input. The
HI-8588-10 device is typically chosen for applications
where external series resistors are required in its lightning
protection circuitry.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
between VCC and Ground. The nominal settings corre-
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TestA and
TestB pins. Unlike the HI-8588, if TestA and TestB are
both One, the HI-8588-10 outputs are pulled low instead
of being tri-stated. This allows the digital outputs of a
transmitter to be connected to the test inputs through
control logic for self-test purposes.
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
TEST
TESTA
TESTB
SQ
LATCH
R
TEST
TESTA
TESTB
FIGURE 1 - RECEIVER BLOCK DIAGRAM
ROUTA
ROUTB
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8588 interfacing an ARINC receive channel
to the HI-6010 which in turn interfaces to an
8-bit bus.
HARDWIRE
OR
{
DRIVE FROM LOGIC
ARINC
Channel
ARINC
Channel
10KΩ
10KΩ
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8588-10
RINA
3
RINB GND
5
15V
1
8
SLP1.5 V+
6 TXAOUT
TX0IN 2
7 HI-8586 3
TXBOUT
TX1IN
GND V-
45
RXD1
RXD0
HI-6010
8 BIT BUS
TXD0
TXD1
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
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