FM24CL16 Просмотр технического описания (PDF) - Ramtron International Corporation

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FM24CL16

16Kb FRAM Se rial 3V Memory

Ramtron International Corporation 

FM24CL16

Diagram Notes

All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read

and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional

relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

SCL

tR

t HIGH

` tF

tLOW

t SP

t SP

t SU:STA

tBUF

SDA

1/fSCL

t HD:DAT

tSU:DAT

Start

Stop Start

tAA

t DH

Acknowledge

Write Bus Timing

SCL

SDA

t SU:STO

t HD:DAT

t HD:STA

t SU:DAT

t AA

Start

Stop Start

Acknowledge

Data Retention (VDD = 2.7V to 3.65V, 85°C)

Parameter

Min

Data Retention

45

Units

Years

Notes

Rev 3.3

Nov. 2005

Page 10 of 13

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